Hardware-Efficient Accelerator for Spiking Neural Networks with Synchronous Spike Storage and Weight Address Control

Abstract

Spiking neural networks (SNNs) are attracting attention for their energy-efficient computation and real-time processing capabilities, as they emulate the time-based signal processing of the human brain. However, prior hardware implementations have the disadvantages of high resource usage and long inference latency. To solve this problem, we present a hardware-efficient FPGA-based SNN architecture. Through voltage scaling, hardware-efficient optimization of synaptic transmission delay, and reformulation of the neuron equation with power-of-two scaling, hardware resources are greatly reduced. Furthermore, the synchronous spike storage and controller modules are introduced to simplify the data path. The proposed design was implemented on the XC7Z7020 board, achieving an inference latency of 1.41 ms/image and a 103.8× speedup over the CPU on the MNIST dataset with only a 0.3% accuracy drop.