A Single-Ended NRZ Transceiver in 28-nm CMOS Process with Power-Isolated LVSTL Driver and 3-Stage Sampler for Low-Power Memory Interfaces

Abstract

This paper presents a low-power, high-speed nonreturn-to-zero (NRZ) transceiver for low-power memory interfaces. The proposed transceiver (TRX) consists of a singleended transmitter (TX) and receiver (RX), achieving data rates of 15 Gb/s and 12 Gb/s, respectively, each incorporating a 2-tap feed-forward equalizer (FFE) and a 1-tap direct decision feedback equalizer (DFE). The quarter-rate clocking architecture, enhancing timing margin and power efficiency, is adopted in both the transmitter and the receiver. The TX utilizes a low voltage swing terminated logic (LVSTL) driver operating at a 0.5-V VDDQ and employs a 2-tap de-emphasis FFE to compensate for channel loss. The RX incorporates a 3-stage sampler structure. The 1-tap direct DFE effectively compensates for inter-symbol interference (ISI) caused by channel loss, improving signal integrity. Fabricated in a 28-nm CMOS process, the TRX achieves an energy efficiency of 0.64 pJ/bit at 15 Gb/s in the TX and 0.043 pJ/bit at 12 Gb/s in the RX, providing a solution for high-speed and low-power memory interfaces.