Design of NRZ/PAM-3/PAM-4 Tri-Mode Single-Ended Transmitter for Next-Generation Memory Interfaces

Jiao Jiang; Joo-Hyung Chae

doi:10.23075/jicas.2024.10.4.006

Jiao Jiang Kwangwoon University
Joo-Hyung Chae Kwangwoon University

DOI: https://doi.org/10.23075/jicas.2024.10.4.006

Keywords: Feed-forward equalizer (FFE), level separation mismatch ratio (RLM), transmitter, tri-mode ZQ calibration

Abstract

This paper presents a single-ended voltage-mode transmitter for next-generation memory interfaces, supporting three signaling modes: non-return-to-zero (NRZ), three-level pulse amplitude modulation (PAM-3), and four-level pulse amplitude modulation (PAM-4). Utilizing the same output driver, the tri-mode transmitter effectively reduces the development cycle and associated costs for intellectual property (IP) development. Firstly, based on the mode selection signal, two mode selectors determine which data are passed to the tri-mode driver, outputting the data in either NRZ, PAM-3, or PAM-4 signaling. Secondly, 2-tap feed-forward equalizers (FFE) are separately applied to the three modes, compensating for signal distortions caused by losses in signal transmission through the channel based on different FFE encodings. A seven-step four-point ZQ calibration with offset cancellation is implemented to improve the level separation mismatch ratio. Designed using 65-nm CMOS technology, the transmitter achieved data rates of 16-Gb/s in NRZ mode, 24-Gb/s in PAM-3 mode, and 32-Gb/s in PAM-4 mode.

Author Biographies

Jiao Jiang, Kwangwoon University

Jiao Jiang is currently pursuing her M.S. degree at the department of Electronics and Communications Engineering, Kwangwoon University, Seoul, Korea.

Her research interests include high-speed wireline interface.

Joo-Hyung Chae, Kwangwoon University

Joo-Hyung Chae received his B.S. and Ph.D. degrees in Electrical Engineering from Seoul National University, Seoul, South Korea, in 2012 and 2019, respectively.

In 2013, he joined SK hynix, Icheon, South Korea, as an intern at the Department of LPDDR Memory Design. From 2019 to 2021, he was with SK hynix, Icheon, South Korea, where his work focused on GDDR memory design. In 2021, he joined Kwangwoon University, Seoul, South Korea, where he is currently an Assistant Professor of Electronics and Communications Engineering.

His research interests include the design of high-speed and low-power I/O circuits, clocking circuits, memory interfaces, and mixed-signal in-memory computing.

Dr. Chae received the Doyeon Academic Paper Award from the Inter-University Semiconductor Center (ISRC), Seoul National University, in 2020.

Homepage : https://sites.google.com/view/jhchae/member/professor

Design of NRZ/PAM-3/PAM-4 Tri-Mode Single-Ended Transmitter for Next-Generation Memory Interfaces

Abstract

Author Biographies

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