Design of a 12 – 14.5 GHz Digitally-Controlled Oscillator for Ultra-low-jitter PLL

  • Joo Eun Bang KAIST
  • Yong Woo Jo KAIST
  • Seo Jin Choi KAIST
  • Jae Hyuk Choi KAIST
Keywords: Delta-Sigma Modulator(DSM), Digital-to-Analog Converters(DAC), Digitally-Controlled Oscillator(DCO), LC-VCO, Phase-Locked Loop, Phase noise, Sub-sampling

Abstract

The DCO was designed for the ultra-low-jitter digital sub sampling PLL. To suppress the enormous amount of quantization noise, very fine frequency resolution is critical. Also, phase noise of the LC VCO itself is crucial for ultra-low-jitter applications. For the high-performance LC VCO design, understanding of the basic insight of the oscillator is needed. The DCO consists of string type RDAC, MASH 1-1 DSM, and CMOS-type cross coupled LC VCO. The frequency resolution is significantly increased by using DSM. The proportional path has the resolution of 17-bit, while the integral path has the resolution of 18-bit. The DSM is operating at 400MHz and its quantization noise is canceled by the 2nd order low pass filter at the output of the DAC. By adopting 2nd order noise shaping, quantization noise at PLL out is negligible. The DAC designed with a string resistor topology for its design simplicity and relieved target specifications. The DCO has 12-14.5GHz of frequency tuning range. The phase noise at 1MHz offset frequency is -109dBC/Hz at 14GHz output. The average power consumption is 5.5mW. Calculated FOM at 1MHz offset frequency is -184.5dB.

Published
2020-12-31
Section
Articles