Design of a Low-Quiescent-Current Gate-Pole-Dominant Low-Dropout-Regulator

Joo Eun Bang; Young Hyun Lim; Jae Hyouk Choi

doi:10.23075/jicas.2020.6.3.005

Joo Eun Bang Korea Advanced Institute of Science and Technology
Young Hyun Lim Korea Advanced Institute of Science and Technology
Jae Hyouk Choi Korea Advanced Institute of Science and Technology

DOI: https://doi.org/10.23075/jicas.2020.6.3.005

Keywords: Gate-pole-dominant, High power-supply-rejection-ratio, Low-quiescent-current

Abstract

Recently, for the mobile and internet-of-things applications, the level of integration is getting higher. Low-dropout voltage regulators (LDOs) get popular in integrated circuit design including functions such as reducing switching ripples from high-efficiency regulators, cancelling spurs from other loads, and giving different supply voltages to loads. In accordance with load applications, choosing proper LDOs is important. LDOs can be classified by the types of power MOSEFT, the topologies of error amplifier, and the locations of dominant pole. Analog loads such as voltage-controlled oscillators and analog-to-digital converters need LDOs that have high power-supply-rejection-ratio (PSRR), high accuracy, and low noise. We present a low-quiescent-current fully-integrated LDO that obtains the desired PSRR.

Author Biographies

Joo Eun Bang, Korea Advanced Institute of Science and Technology

Joo Eun Bang (S’18) was born in Busan, South Korea, in 1995. She received the B.S. and M.S. degrees in electrical engineering from the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2018 and 2020, respectively. She is currently pursuing the Ph.D. degree with the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. Her current research interests include low-power and high-performance analog, mixed-signal, and RF integrated circuits for emerging wireless/wired standards.

Young Hyun Lim, Korea Advanced Institute of Science and Technology

Young Hyun Lim (S’14) was born in Gyeongju, Korea, in 1992. He received the B.S. degree in electrical engineering from the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2015, where he is currently pursuing the combined M.S./Ph.D. degree. He was an Intern with Qualcomm, Inc., San Diego, CA, USA, where he was involved in designing the PLLs in the upcoming TRXs. His research interests include low-power and high-performance analog, mixed signal, and RF integrated circuits for emerging wireless/wired standards.

Mr. Lim was the recipient of the IEEE Student Research Preview (SRP) Award for the outstanding poster at ISSCC in 2019, the Korean Government Scholarship (GPF), and the Honorable Mention and the Bronze Prize at the 24^th and 25^th Samsung Human Tech Paper Award in 2018 and 2019, respectively.

Jae Hyouk Choi, Korea Advanced Institute of Science and Technology

Jae Hyouk Choi (S’06–M’11) was born in Seoul, South Korea, in 1980. He received the B.S. degree (summa cum laude) in electrical engineering from Seoul National University, Seoul, South Korea, in 2003, and the M.S. and Ph.D. degrees in electrical and computer engineering from Georgia Institute of Technology, Atlanta, GA, USA, in 2008 and 2010, respectively.

From 2010 to 2011, he was with Qualcomm, Inc., San Diego, CA, USA, where he was involved in designing multi-standard cellular transceivers. In 2012, he joined the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, and served as a faculty member. Since 2019, he has been an Associate Professor at the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea.

Dr. Choi has been a TPC member of the IEEE ISSCC since 2017 and the IEEE ESSCIRC since 2016. He was the country representative of Korea for the ISSCC Far-East region in 2018. His research interests include low-power and high-performance analog, mixed signal, and RF integrated circuits for emerging wireless/wired standards.

Homepage : https://www.icsl.snu.ac.kr/

Design of a Low-Quiescent-Current Gate-Pole-Dominant Low-Dropout-Regulator

Abstract

Author Biographies

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