A 7–8.5 GHz LC Voltage-Controlled Oscillator with –111.7 dBc/Hz Phase Noise at 1-MHz offset for Ultra-Low-Jitter Phase-Locked Loop

  • Yong Woo Jo Korea Advanced Institute of Science and Technology
  • Mun Jae Chae Korea Advanced Institute of Science and Technology
  • Jae Hyouk Choi Korea Advanced Institute of Science and Technology https://orcid.org/0000-0002-3055-8684
DOI: https://doi.org/10.23075/jicas.2023.9.1.001
Keywords: Area-efficient, Jitter, LC-Oscillator, Phase-Locked Loop, Tail Inductor, Voltage-Controlled Oscillator(VCO)

Abstract

This work presents an area efficiency LC voltage-controlled oscillator for an ultra-low-jitter phase-locked loop. Using a 3-turn area-compact spiral, the VCO achieve area-efficient without degrading LC-tank quality factor. The negative transconductance cell was NMOS type so that the start-up was done in 3ns. This work also includes a tail inductor for the noise filtering. As a result, the measured phase noise at 8 GHz was -111.7 dBc/Hz with 1 MHz offset and -134.9 dBc/Hz with 10 MHz offset. The power consumption was only 2.7 mW at 8 GHz. Also, the die area was less than 0.03 mm2.

Author Biographies

Yong Woo Jo, Korea Advanced Institute of Science and Technology

Yong Woo Jo (S’17) was born in Gumi, South Korea, in 1995. He received the B.S. and M.S. degrees in electrical engineering from the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2018 and 2020, respectively. He is currently pursuing the Ph.D. degree with the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. His current research interests include digital PLL and RF integrated circuits for next generation communications.

Mun Jae Chae, Korea Advanced Institute of Science and Technology

Mun Jae Chae was born in Gyeongsan, South Korea, in 1997. He received the B.S. degree in electrical engineering from the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2021. He is currently pursuing the M.S. degree with the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. His research interests include CMOS analog/mixed integrated circuit (IC) designs, especially high-speed clock/frequency generation systems.

Jae Hyouk Choi, Korea Advanced Institute of Science and Technology

Jae Hyouk Choi was born in Seoul, South Korea, in 1980. He received the B.S. degree (summa cum laude) in electrical engineering from Seoul National University, Seoul, in 2003 and the M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 2008 and 2010, respectively. From 2010 to 2011, he was with Qualcomm, Inc., San Diego, CA, USA, where he was involved in designing multi standard cellular transceivers. In 2012, he joined the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, as a Faculty Member. Since 2019, he has been an Associate Professor with the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. His research interests include low-power and high-performance analog, mixed-signal, and RF integrated circuits for emerging wireless/wired standards. Dr. Choi has been a TPC Member of the IEEE International Solid-State Circuits Conference (ISSCC) since 2017 and the IEEE European Solid-State Circuits Conference (ESSCIRC) since 2016. He was the Country Representative of South Korea for the ISSCC Far-East Region in 2018. He has been a Distinguished Lecturer (DL) of the Solid-State Circuits Society (SSCS) since 2020.

Homepage: https://www.icsl.snu.ac.kr/

Published
2023-01-01
How to Cite
Jo, Y. W., Chae, M. J., & Choi, J. H. (2023). A 7–8.5 GHz LC Voltage-Controlled Oscillator with –111.7 dBc/Hz Phase Noise at 1-MHz offset for Ultra-Low-Jitter Phase-Locked Loop. Journal of Integrated Circuits and Systems, 9(1). https://doi.org/10.23075/jicas.2023.9.1.001
Issue
Vol 9 No 1 (2023)
Section
Articles

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