A 40-Gb/s 0.78-pJ/bit PAM-4 Transceiver with Unterminated Signaling for Chiplet Interface in 28-nm CMOS

Abstract

In this paper, we propose a 40-Gb/s single-ended PAM-4 unterminated transmitter for chiplet interface in next-generation high-performance computing (HPC) and artificial intelligence (AI) accelerator systems. With recent advancements in heterogeneous integration, bandwidth density and energy efficiency have emerged as critical metrics for die-to-die (D2D) communications. While previous unterminated PAM-4 drivers required three voltage sources, using multiple supply rails increases design complexity and cost in practical implementations. To address this issue, the proposed transceiver implements an unterminated PAM-4 driver that achieves high data-rate and power efficiency using a single voltage source. To minimize the power consumption of PAM-4 signaling, the driver adopts an N-over-N architecture. In this paper, a simulation was performed using the on-chip channel. Designed using a 28-nm CMOS process, the transmitter achieves a power efficiency of 0.78 pJ/bit at 40 Gb/s and maintains a stable eye-opening even with a channel loss of -0.8 dB at the Nyquist frequency.