View of A 40-Gb/s 0.78-pJ/bit PAM-4 Transceiver with Unterminated Signaling for Chiplet Interface in 28-nm CMOS

Return to Article Details A 40-Gb/s 0.78-pJ/bit PAM-4 Transceiver with Unterminated Signaling for Chiplet Interface in 28-nm CMOS Download Download PDF