Ku-Band Class-J CMOS Power Amplifier Using Sequential Harmonic Impedance Technique

Abstract

This paper presents a Ku-Band Class-J CMOS Power Amplifier (PA) designed in a 65-nm CMOS process using a single-stage differential cascode topology. To overcome the complexity of the output matching network for high-efficiency Class-J operation, a sequential harmonic impedance technique using a parallel-resonance-based transformer is proposed. This technique simplifies the design process by sequentially optimizing the fundamental and harmonic impedances. Furthermore, a Cold-FET linearizer is utilized to compensate for AM-AM distortion, while a second-harmonic shorting network leveraging the virtual ground of the differential structure is employed to suppress AM-PM distortion to less than 1.6°. Simulation results demonstrate that the PA achieves a peak power-added efficiency (PAE) of 40.2 %, a saturated output power (P_sat) of 21.3 dBm, and a large signal gain of 15.2 dB at 14 GHz. These results verify that the PA simultaneously satisfies the requirements for high efficiency and linearity.