Ka-Band CMOS Power Amplifier Based on Asymmetric Parallel Power Combiner with Shared Linearizer

Abstract

This paper presents a Ka-Band CMOS cascode power amplifier (PA) designed in a 65-nm CMOS process, featuring a cold-FET linearization technique applied to a one-sided cascode cell within each differential pair. The proposed PA employs a differential cascode topology to enhance gain, along with neutralization capacitors for stability. To maximize output power, a parallel-combining transformer is employed. Crucially, this output matching network adopts an intentional asymmetric structure to cancel out the phase deviation caused by the linearization technique, thereby optimizing both power and linearity. Simulation results at 28 GHz demonstrate a peak power-added efficiency (PAE) of 35 % and a saturated output power (P_sat) of 22.8 dBm, with a chip area of 0.47 mm². Furthermore, the proposed linearization technique improves the OP_1dB by 2 dB and suppresses AM-PM distortion to less than 2.6°.