A Phase-Domain Analysis of a Sub-Sampling PLL with a Second-Order Loop Filter

Abstract

This paper presents a phase-domain analysis of a Sub-Sampling Phase-Locked Loop (SSPLL) that combines a Frequency-Locked Loop (FLL) with a sub-sampling core loop. The reported phase-noise and loop-performance results are primarily analytical and MATLAB-based predictions rather than hardware measurements. A condition-based frequency-lock detector (FLD) governs the handoff between the FLL and the sub-sampling core loop: the FLL is disabled only after the frequency-error metric remains below a lock threshold for a prescribed number of reference cycles, and it is re-enabled if an upper loss-of-lock threshold is exceeded. The zero and pole frequencies of the second-order loop filter are explicitly defined, and a normalized time-domain illustration is added to show frequency pulling, control-voltage settling, and FLD-qualified handoff. A single-corner transistor-level (schematic) simulation of the SSPLL combining an FLL and a sub-sampling core loop is additionally provided as a preliminary circuit-level check, confirming that the core loop maintains lock once the FLL is disabled. The phase-domain model predicts a loop bandwidth of approximately 5.65 MHz, a phase margin of 50.2 degrees, phase noise of -118.8 dBc/Hz at 10 kHz offset, and -133.8 dBc/Hz at 10 MHz offset. A comparison with measured SSPLLs is provided to position these predictions and to make the present work's validation limits explicit.