Comparison of 3T2C Embedded DRAM in 28nm FD-SOI and Low Power Plus for Energy-Efficient Computing in Memory Architecture

Abstract

This paper presents a comparative analysis of a 3T 2C Embedded DRAM (eDRAM) bitcell fabricated in 28-nm LPP and FD-SOI processes for energy-efficient Computing-in-Memory (CIM) applications. eDRAM provides dense charge domain storage that is directly exploited for compact analog Multiply-And-Computation (MAC) operation in CIM arrays. The proposed cell employs a metal-oxide-metal (MOM) capacitor to achieve high capacitance density without additional process steps. Post-layout simulations and Monte Carlo analyses were conducted to evaluate the effects of the process and temperature variations and capacitive coupling on data retention and analog compute accuracy. Results show that the FD-SOI process provides enhanced retention characteristics and larger voltage margins owing to stronger capacitive coupling and reduced substrate leakage enabled by the buried oxide (BOX) layer.