Low-Complexity Referenceless Clock and Data Recovery with a Novel Alexander Phase-Frequency Detector

Abstract

This paper proposes a low-complexity referenceless clock and data recovery (CDR) circuit for high-speed serial communication systems. Its core contribution is a novel Alexander phase-frequency detector (APFD) that achieves a wide frequency acquisition range with minimal hardware overhead. The proposed APFD generates its frequency tracking signals by utilizing a single inverter on the conventional Alexander phase detector’s (APD) UP signal, eliminating the need for complex pattern decoding logic. We theoretically analyze the operational principle by modeling the probabilistic behavior of the detector's outputs, and our analysis is successfully verified through simulations, which show excellent correlation with the derived mathematical model. This APFD is integrated into a comprehensive 32 Gb/s quarter-rate CDR architecture. To ensure robust performance, the system incorporates an adaptive loop gain controller based on the signsign LMS algorithm and a direct proportional path with a deadzone mitigation technique to enhance high-frequency jitter tracking. By drastically simplifying the frequency detection mechanism, this work presents a promising solution for nextgeneration wireline transceivers that offers significant advantages in terms of circuit area and power efficiency.