Implementation and Characterization of a Digital Phase-Locked Loop (DPLL) in 65-nm CMOS Technology

Abstract

This paper presents an experimental study on the influence of digital loop filter (DLF) gains K_P,PLL and K_I,PLL on the dynamic and noise performance of a 65 nm CMOS digital phase-locked loop (DPLL). By varying K_P,PLL and K_I,PLL across a range of values, the resulting changes in loop bandwidth, lock time, phase noise, and output jitter were measured. Silicon prototype measurements demonstrate that increasing K_P,PLL reduces lock time but may introduce peaking in the closed-loop response, whereas increasing K_I,PLL enhances low-frequency phase error suppression at the expense of slower settling. Under optimal gain settings, silicon measurements show an output spur level as low as −68.80 dBc and an RMS jitter of 0.638 ps, confirming excellent noise and spur performance.