Wordline Driver for Processing-in-Memory Using the Input Bit-Slicing Method

Abstract

The von Neumann bottleneck, caused by the performance gap between memory and processing units, has become a critical issue in modern computing systems. This bottleneck fundamentally limits system throughput and energy efficiency. It becomes particularly critical as data-centric applications continue to demand higher bandwidth and faster access. To overcome this limitation, analog processing-in memory has emerged as a promising candidate to address this challenge. In this work, we designed a wordline driver for processing-in-memory systems that use the input bit-slicing method, where fixed-length binary pulses serve as inputs. The proposed wordline driver was fabricated using the TSMC 180 nm CMOS logic process. Measurement results confirm that the wordline driver successfully generates 4-bit fixed-length binary pulses at the desired voltage levels, ensuring reliable wordline activation during input bit slicing. To provide a system-level context, we also describe a successive integration-and-rescaling neuron fabricated on the same 180 nm CMOS wafer. The integration of the proposed driver with this neuron was established in our prior work, reinforcing the claim that it effectively supports robust input bit-slicing operations in processing-in-memory architectures. Ultimately, these results confirm the feasibility of the proposed wordline driver for use in practical analog processing-in-memory systems.