Design Methodology for Capacitively Coupled Continuous-time Delta-sigma Modulator

  • Chae Gang Lim Korea University
  • Chul Woo Kim Korea University
DOI: https://doi.org/10.23075/jicas.2022.8.1.003
Keywords: CCIA, Chopping, CTDSM, High-lignearity

Abstract

This paper presents a design methodology for high-linearity capacitively coupled (CC) continuous-time delta-sigma modulator (CTDSM). The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 uA at a 1.8 V supply. The proposed CC-CTDSM has a 19.4 nV/√Hz input-referred noise density, 1.9 uV offset, 0.08\% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mVpp.

With -110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique.

Author Biographies

Chae Gang Lim, Korea University

Chae Gang Lim (S’14) received the B.S. degrees in electrical engineering from Korea University, Seoul, South Korea, in 2014, where he is currently working toward an integrated M.S. And Ph. D. degree.
In 2017, he was a Visiting Researcher at the University of Texas at Austin, TX, USA. He received the 21st Korea Semiconductor Design Contest enterprise special prize (Cadence) in 2020. His research interests include sensor readout ICs and oversampling ADCs.

Chul Woo Kim, Korea University

Chul Woo Kim (S’98-M’02-SM’06) received the B.S. and M.S. degrees in electronics engineering from Korea University in 1994 and 1996, respectively, and a Ph. D. in electrical and computer engineering from the University of Illinois at Urbana-Champaign, IL, USA, in 2001. In 1999, he worked as a summer intern at the Design Technology at Intel Corporation, Santa Clara, CA. In May 2001, he joined IBM Microelectronics Division, Austin, TX, where he was involved in Cell processor design. Since September 2002, he has been with the School of Electrical Engineering, Korea University, where he is currently a Professor. He was a Visiting Professor at the University of California at Los Angeles in 2008 and at the University of California at Santa Cruz in 2012. He is a coauthor of two books, namely, CMOS Digital Integrated Circuits: Analysis and Design (McGraw Hill, 4th edition 2014) and High-Bandwidth Memory Interface (Springer, 2013). His current research interests are in the areas of wireline transceiver, memory, power management and data converters. Dr. Kim received the Samsung HumanTech Thesis Contest Bronze Award (1996), the ISLPED Low-Power Design Contest Award (2001, 2014), the DAC Student Design Contest Award (2002), SRC Inventor Recognition Awards (2002), the Young Scientist Award from the Ministry of Science and Technology of Korea (2003), the Seoktop Award for excellence in teaching (2006, 2011) and ASP-DAC Best Design Award (2008) and Special Feature Award (2014), Korea Semiconductor Design Contest: Prime Minister Award (2016). He served on the Technical Program Committee of the IEEE International Solid-State Circuits Conference and as a Guest Editor for IEEE Journal of Solid-State Circuits. He is currently on the editorial board of IEEE Transactions on VLSI Systems and the Chair of the SSCS Seoul Chapter. He has been elected as Distinguished Lecturer of the IEEE Solid-State Circuits Society for 2015-2016.

Homepage : https://kilby.korea.ac.kr/

Published
2021-12-30
How to Cite
Lim, C. G., & Kim, C. W. (2021). Design Methodology for Capacitively Coupled Continuous-time Delta-sigma Modulator. Journal of Integrated Circuits and Systems, 8(1). https://doi.org/10.23075/jicas.2022.8.1.003
Issue
Vol 8 No 1 (2022)
Section
Articles