Word-line and Charge-pump modeling of NAND Flash using Standard CMOS Logic Process
The industry has increased the word line layer to improve the density of 3D NAND flash. As the word line layer increases, the energy consumed to generate the boosted word line voltage has also increased. In 3D NAND flash, understanding the block configuration and operation of a voltage step-up system with high energy consumption should be preceded to implement a 3D NAND flash with low energy consumption.
This study presents a conventional voltage step-up system for triple-level cell 3D NAND flash to understand operation and classify energy consumption. The conventional voltage step-up system for a 56 word line layer is fabricated in 180nm UHV process and it consumes 141.15nJ from a 2.2V during 1 unit of program pulse and verify period.