Design and Optimization of Centimeter-Scale Long-Reach On-Chip Interconnect for Wafer-Level Computing

Abstract

This paper investigates two on-chip interconnect structures, a single-metal (Single M9) and a vertically stacked (M9/M8), for 100 Gb/s, 20mm links in Wafer-Level Computing (WLC) or Wafer-Scale Integration (WSI) systems, targeting an insertion loss below -15 dB at 25 GHz. Counterintuitively, 3D EM simulations reveal that the simpler single M9 channel is superior, achieving a -14.5 dB insertion loss, while the stacked structure exhibits a worse loss of -16.4 dB. This performance inversion is attributed to the dominance of dielectric loss over conductor loss in the stacked structure at high frequencies. System-level link simulations verify this finding, showing the single M9 channel achieves an open 100 Gb/s PAM-4 eye with a fixed FFE, a condition under which the stacked channel fails. This work highlights that high-frequency interconnect design involves a complex trade-off, demonstrating that a holistic analysis of both conductor and dielectric loss mechanisms is critical for achieving a truly optimal solution.