A Design Technique for Highly Parallel Pseudo-Random Ternary Sequences Generators

Abstract

This paper introduces a design technique and an optimized architecture for pseudo-random trit sequence (PRTS) generation and checking, aimed at high-speed serial communication systems such as PAM-3 transceivers. Unlike PRBS generators that rely on modulo-2 arithmetic, PRTS generation requires modulo-3 operations, which introduce additional design complexity. To address this, we propose a transition matrix-based framework for parallel PRTS generation, enabling efficient high-throughput sequence construction while remaining compatible with standard CMOS design methodologies. The circuits are designed in a 28-nm CMOS process using a standard-cell design flow. The generator achieves 72Gb/s operation at 1.89mW with an area of 0.00045 mm², while the checker consumes 1.64mW and occupies only 0.00218 μm². The proposed solution provides nearly a twofold improvement in both area and power efficiency when compared with a previous work.