Design of 2.5-Gb/s Parallel PRBS Generator and 4-Gb/s Area Efficient PRBS Checker in 65-nm CMOS Process

Abstract

A pseudo-random binary sequence (PRBS) pattern is widely used in various applications requiring random data sequences. This paper describes the design of a parallel PRBS generator and checker. The parallel PRBS generator produces eight outputs where each output has a PRBS-7 pattern with a period of 2⁷–1, and the PRBS checker verifies if the incoming data is a PRBS-7 pattern. In the PRBS checker, a method of creating the same reference PRBS pattern as the incoming data is applied using a synchronization detection circuit that finds a unique pattern in the input data stream. The PRBS checker includes data and error counters, and they count the number of input data and bit errors that occur during one cycle of the PRBS-7 pattern. This design was implemented with a 65-nm CMOS process, and the PRBS generator and checker occupy an area of 75×15 μm² and 75×45 μm², respectively. It was verified that the PRBS generator operated up to 2.5 Gb/s and the PRBS checker accurately counted the bit error at 4 Gb/s.