Design of a low noise Analog Front End System for Sonar Signal Conditioning Receiver

Sonar Signal Conditioning Receiver

  • Jong Wan Jo Sungkyunkwan University
  • Sung Jin Kim Sungkyunkwan University
  • Muhammad Riaz Ur Rehman Sungkyunkwan University
  • Khuram Shehzad Sungkyunkwan University
  • Young Woo Park Sungkyunkwan University
  • Young Gun Pu Sungkyunkwan University
  • Dong Hun Lee Agency for Defense Development
  • Hyung Moon Kim Agency for Defense Development
  • Kang Yoon Lee Sungkyunkwan University
DOI: https://doi.org/10.23075/jicas.2020.6.1.001
Keywords: Band pass filter, Low noise, Parallel-to-serial interface, Receiver, Sigma-Delta ADC, Sonar sensor

Abstract

This paper presents the design of a low noise analog front end system for sonar signal conditioning receiver with Parallel to Series Interface in very noisy environments. When measuring distances in the ocean through sonar, the input signal level to the receiver can change drastically depending on the distance between the transmitter and objects. Thus, a receiver with low sensitivity and a wide dynamic range is proposed in this work. In order to minimize the Input-Referred (IR) noise for the high sensitivity of the receiver, a low noise pre-amplifier is proposed and implemented, ultimately achieving a noise of 11 nV/√Hz at 50 kHz. The decimation factor of the digital filter placed after the SDM in the SD ADC can be controlled so as to reduce the power consumption. Through the use of these techniques in the SD ADC, we can implement reconfigurable sampling rates from 1.5 MS/s to 12.5 MS/s with low power consumption. In order to overcome the limitation of the number of pins for sensor application, a Parallel-to-Serial (P2S) interface is proposed and designed in the receiver. The Low Noise receiver in this paper is implemented in a 0.18 μm CMOS process and the die area is 14.44 mm2. The total power consumption of this chip under a supply voltage of 2.4 V is 46.8 mW. The measured sensitivity and dynamic range are -100 dBV and 100 dB, respectively. The measured SNDR at the output of the SD ADC is 82.02 dB when the input signal frequency and sampling frequency are 7 kHz and 6.25 Msps, respectively.

Author Biographies

Jong Wan Jo, Sungkyunkwan University

Jong Wan Jo received his B.S. degree from the Department of Electronic Engineering at Cheongju University, Cheongju, Korea, in 2018, where he is currently working toward the M.S degree in School of Information and Communication Engineering, Sungkyunkwan University His research interests include Wireless Power Transfer systems and Power Management IC.

Sung Jin Kim, Sungkyunkwan University

Sung Jin Kim received his B.S. degree from the Department of Electronic Engineering at Inje University, Kimhea, Korea, in 2014, where he is currently working toward the Combined Ph.D. & M.S degree in School of Information and Communication Engineering, Sungkyunkwan University. His research interests include CMOS RF transceiver and wireless power transfer systems.

Muhammad Riaz Ur Rehman, Sungkyunkwan University

Muhammad Riaz ur Rehman received his B.S. Computer Engineering and M.S. Electrical Engineering from University of Engineering and Technology, Taxila, Pakistan, in 2007 and 2011, respectively. From 2007 to 2016, he was with Horizon Tech Services, Islamabad, Pakistan, where he was a Senior Engineer of the Product Development Division. He is currently working toward Ph.D. degree in School of Information and Communication Engineering at Sungkyunkwan University, Suwon, Korea. His research interests include implementation of analog/digital mixed-mode VLSI system design, power integrated circuits, CMOS RF transceiver and analog integrated circuits

Khuram Shehzad, Sungkyunkwan University

Khuram Shehzad received his B.S degree in Electrical Engineering with specialization in Telecommunication from Government College University, Faisalabad, Pakistan. He is currently pursuing his Combined MS & Ph.D degree in Electrical and Computer Engineering from College of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea. His research interests include design of high performance data converters including SAR and SD ADC; CMOS RF Transceiver.

Young Woo Park, Sungkyunkwan University

Young Woo Park received his B.S. degree from the Department of Electronic Engineering at sungkyul University, Anyang Korea, in 2018, where he is currently working toward the M.S degree in School of Information and Communication Engineering, Sungkyunkwan University His research interests include Wireless Power Transfer systems and Power Management IC.

Young Gun Pu, Sungkyunkwan University

Young Gun Pu received his B.S., M.S. and Ph.D. degrees from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2006, 2008 and 2012, respectively. His research interests are focused on CMOS fully integrated frequency synthesizers and oscillators and on transceivers for low-power mobile communication.

Dong Hun Lee, Agency for Defense Development

Dong Hun Lee received the B.S. and M.S. degrees in electronic and electrical engineering from Kyungpook National University, Daegu, South Korea, in 1994 and 1996, respectively, and Ph.D. degrees in electronic and electrical engineering from Pusan National University, Busan, South Korea, in 2017. Since 1996, he has been a Principal Researcher at the 3rd Directorate, Matitime Technology Research Institute, Agency for Defense Development, Changwon, South Korea. His main research interests include the area of RADAR/SONAR signal processing, digital signal & array signal processing, and power electronics system & circuit design.

Hyung Moon Kim, Agency for Defense Development

Hyung Moon.Kim received the B.S. and M.S. degrees in Electrical, Electronic and control Engineering from Changwon University, Changwon, South Korea, in 2000 and 2002, respectively. He is currently working toward the Ph.D. degree at the Power Electronics Laboratory Department of Electrical Engineering at Changwon University, Changwon, South Korea. He worked at Korea Aerospace Industries,LTD, Sacheon, South Korea from 2001 to 2006. Since 2006, he has been a Senior Researcher at the 3rd Directorate, Matitime Technology Research Institute, Agency for Defense Development, Changwon, South Korea. His research interests include SONAR System, Flight Control System, and Embedded System.

Kang Yoon Lee, Sungkyunkwan University

Kang Yoon Lee received the B.S. M.S., and Ph.D. degrees in the School of Electrical Engineering from Seoul National University, Seoul, Korea, in 1996, 1998, and 2003, respectively. From 2003 to 2005, he was with GCT Semiconductor Inc., San Jose, CA, where he was a Manager of the Analog Division and worked on the design of CMOS frequency synthesizer for CDMA/PCS/PDC and single-chip CMOS RF chip sets for W-CDMA, WLAN, and PHS. From 2005 to 2011, he was with the Department of Electronics Engineering, Konkuk University as an Associate Professor. Since 2012, he has been with School of Information and Communication Engineering, Sungkyunkwan University, where he is currently a Professor. His research interests include implementation of power integrated circuits, CMOS RF transceiver, analog integrated circuits, and analog/digital mixed-mode VLSI system design.

Homepage : http://www.iclab.co.kr/

Published
2020-12-23
How to Cite
Jo, J. W., Kim, S. J., Rehman, M. R. U., Shehzad, K., Park, Y. W., Pu, Y. G., Lee, D. H., Kim, H. M., & Lee, K. Y. (2020). Design of a low noise Analog Front End System for Sonar Signal Conditioning Receiver. Journal of Integrated Circuits and Systems, 6(1). https://doi.org/10.23075/jicas.2020.6.1.001
Issue
Vol 6 No 1 (2020)
Section
Articles