A 5.8 GHz DSRC Wake-Up Receiver with an Intelligent Digital Controller

Abstract

In this paper, we introduce a high reliability radio frequency wake-up receiver (WuRx) for electronic toll (TEC) applications. As a final stage, an intelligent digital controller (IDC) is proposed to improve the reliability of WuRx and replace complex analog blocks. IDC achieves high reliability and accuracy by detecting and ensuring the configurable and consecutive number of wake-up signal cycles before activating power-hungry RF transceiver. Presented self-hibernation technique reduces current consumption from IDC and range communication (RC) oscillators during the non-wake-up time. To consider frequency variation of the wake-up signal and increasing WuRx accuracy, a digital hysteresis is included. A watch-dog timer is integrated for IDC self-recovery, to avoid uncertainties due to poor and false wake-up. During wake-up, The digital controller uses 34.62 nW and consumes 38.47 nA at  0.9 V supply. In self-hibernation mode, the current is reduced to 9.7 nA. It can be fully synthesized with 809 gates, and implementation at a 180 nm CMOS process in 94 x 82 μm² area. The measured energy consumption at WuRx is 2.48 μW, and the sensitivity is -46 dBm, the chip area is 0.484 mm².