A Fractional-N ADPLL-Based GFSK Modulator with ADC-Assisted TDC and DCO Gain Calibration

Abstract

This paper proposes a Fractional-N ADPLL-based GFSK modulator for BLE/IoT applications. The proposed system employs an ADC-assisted coarse-to-fine TDC and achieves wide modulation bandwidth without loop bandwidth constraints through two-point modulation (TPM). However, modulation accuracy can be degraded by quantization error (QE) from the delta-sigma modulator (DSM) required for fractional-N operation, TDC nonlinearity, and gain mismatch between the TPM slow and fast paths. Noting that these issues must be resolved sequentially, this paper proposes a sequential calibration flow that first corrects the phase-measurement path before compensating the modulation gain. Background TDC gain calibration removes DSM QE using sign-sign LMS, foreground TDC nonlinearity calibration compensates TDC nonlinearity through 52 sub-zone-based bias code correction, and DCO gain calibration corrects slow/fast path gain mismatch in real time using a fast-converging error-sign algorithm. The proposed modulator is designed in Samsung 28-nm CMOS with a 4.801-GHz DCO operating frequency, which is divided by two to generate a 2.4-GHz BLE RF output. It is designed and verified through post-layout simulation at a 1.0-V supply voltage, consuming 12.42 mW and occupying a 0.4135-mm² core area. Through TDC nonlinearity calibration, the RMS jitter is reduced from 474.6 fs to 440.7 fs and the fractional spur is improved by 2.95 dB, achieving a final FSK error of 2.83%, confirming the effectiveness of the proposed calibration-based GFSK modulation scheme.