A 6-Bit 2GS/s Sampling-Rate 27.8fJ/Conversion-Step 610-μm2 Successive Approximation Register Time-to-Digital Converter

Abstract

This paper proposes a small-area, low-power, and high-speed 6-bit SAR time-to-digital converter (TDC) for time interleaved ADCs. The proposed architecture utilizes a selective delay tuning (SDT) cell to achieve a relatively large reference time step (TLSB) of 4 ps. A TLSB of 4 ps provides sufficient margin to ensure that the SAR TDC’s performance remains dominant over the jitter from voltage-to-time converter (VTC) and TDC delay line thereby preventing SNDR degradation. Fabricated in a 28nm CMOS process, the proposed TDC occupies an active area of only 610 um2. Proposed SAR TDC consumes 2.8mW from a 0.9V supply voltage. At a sampling rate of 2 GS/s, the design achieves an SNDR of approximately 36 dB. The proposed TDC demonstrates a compact area compared to prior arts and achieves a Nyquist FoMW of 27.8 fJ/conv-step.