A GaN Gate Driver with Integrated Protection Circuit

Abstract

This paper proposes a gate driver IC with integrated protection circuits to enhance reliability in high speed power conversion systems. Although GaN power devices are widely adopted to achieve high power density and high conversion efficiency, their relatively immature technology and limited robustness necessitate the use of dedicated protection circuits.

The proposed gate driver employs a separated output buffer structure to prevent short-circuit current during switching transitions and allows independent adjustment of turn-on and turn-off times through external gate resistors. In addition, a low-power hysteretic under voltage lock-out (UVLO) circuit is incorporated to ensure stable operation during power-up and power-down processes while minimizing static current consumption. To suppress false triggering caused by switching noise, a leading edge blanking technique is applied in the over current protection (OCP) scheme. Furthermore, a fault reset time–based protection mechanism is introduced to mitigate fault chattering resulting from repetitive over-current events.