A 0.0031-mm2 6-Bit 400-MS/s Charge-Injection DAC Based Loop Unrolled Asynchronous Successive Approximation Register ADC

Abstract

This paper presents a 6-bit charge-injection DAC based loop unrolled SAR (ci-LU SAR) ADC targeting high speed and area-efficient column readout for highly parallel computing-in-memory (CIM) macros. To reduce the dominant DAC area overhead in prior LU SAR ADCs, the proposed architecture replaces the conventional CDAC with a charge injection DAC (ciDAC) while preserving the sequential domino-style comparator operation of LU SAR conversion. A self-calibrating offset-cancellation scheme is applied to each comparator to mitigate comparator offset mismatch, which is critical in multi-comparator LU architectures. Implemented in 65-nm CMOS, the ADC achieves 400 MS/s with a 1.0-V supply while occupying 0.003157 mm2 core area, where the DAC network accounts for only 11.3% of the core area. Post-layout simulations show 35.73-dB SNDR and 47.86-dB SFDR at Nyquist input, with 3.36-mW power consumption, 168 fJ/conversion-step Walden FoM, and 5.64-bit ENOB.