Total-Ionizing Dose Effects in CMOS Operational Amplifiers with NMOS and PMOS Differential Pairs

Abstract

This paper investigates the impact of total ionizing dose (TID) effects on two-stage CMOS operational amplifiers employing NMOS and PMOS differential input pairs. Previously reported TID-induced threshold voltage shifts for a 180-nm CMOS process are adopted and applied at the circuit level through controlled gate voltage offsets for a fair comparison under identical design constraints. The transistor width and length are fixed, and the effective device size is adjusted by varying the number of transistor fingers to match bias conditions and power consumption between the two amplifier configurations. Circuit-level simulations are performed under a TID condition of 125 krad (SiO₂) and compared with pre-irradiation baseline results. The results show that both NMOS and PMOS differential pair amplifiers maintain stable operation without functional failure. Key small-signal performance metrics, including DC gain, bandwidth, and phase margin, exhibit only moderate changes while stable operation is preserved after TID exposure. In contrast, power consumption shows a more noticeable increase, particularly in the NMOS-input amplifier, reflecting a stronger sensitivity of bias current to TID-induced device degradation.