Fill Factor Preservation in Front-Side Illuminated Single-Photon Avalanche Diode Arrays Using External Routing

Abstract

In recent years, Back-Side Illumination (BSI) has emerged as a prominent configuration for Single-Photon Avalanche Diode (SPAD) arrays, offering excellent photon detection probability (PDP). However, this comes at the cost of high fabrication complexity, reduced yield, and even degraded PDP at certain wavelengths. As a result, Front-Side Illumination (FSI), which implements the SPAD in a standard CMOS process, remains a practical and attractive alternative. In FSI-based SPAD systems, components such as quenching circuits, counters, and TDCs typically reduce the fill factor of individual pixels or the overall array. This work proposes a novel routing scheme that enables area-intensive digital components to be placed outside the array boundary. The proposed structure preserves the fill factor at both the pixel level (4.48%) and the array level (5.19%), compared to the intrinsic SPAD fill factor (5.84%), while successfully demonstrating full system functionality through pattern projection measurements.