A First-Order Noise-Shaping SAR ADC
First-Order Fully-passive Noise-Shaping SAR ADC
Keywords:
Analog-to-Digital Converter(ADC), Noise Shaping(NS), Successive Approximation register(SAR)
Abstract
This paper presents a first-order noise shaping (NS) successive approximation register (SAR) ADC. To reduce circuit complexity, the NS-SAR architecture uses a first-order passive integrator to construct a robust circuit against PVT variation. In a 65-nm CMOS process, the prototype occupies 0.013 mm2 area and consumes only 0.5 mW at sampling frequency of 150-MHz. The proposed first-order NS-SAR ADC achieves the maximum SNDR of 68 dB with oversampling ratio (OSR) of 4 and the peak value of 172.3 dB Schreier FoM (FoMS).
Published
2020-07-01
How to Cite
Oh, Y. G., & Chae, H. I. (2020). A First-Order Noise-Shaping SAR ADC. Journal of Integrated Circuits and Systems, 6(3). https://doi.org/10.23075/jicas.2020.6.3.003
Issue
Section
Articles