Design of a Reconfigurable Multiplier with Variable-Precision
Multipliers remain as a key computational element in numerous high-performance digital systems including the upcoming Machine Learning (ML) hardware and contribute to the overall performance of the system. In this paper, we introduce a variable-precision reconfigurable multiplier and compare the performance against the more conventional fixed-precision multiplier in terms of power dissipation and propagation delay by deploying an FIR filter as our test-bed. The proposed multiplier has enhanced performance in terms of power reduction by 64%, area reduction by 48% and furthermore 60% improvement in propagation delay behavior. The reconfigurable multiplier was implemented using Magnachip / SK Hynix 0.35um process and a 3.3V supply voltage. An FPGA Basys3(xc7a35tcpg-236L) board was used to verify the performance and function of the parallel operation of the proposed multiplier. The Result was a 4-bit input through the FPGA and a chip. The result from that input represents the propagation delay of the multiplier operation, results indicated a worst-case propagation delay for 22.5ns.