Design of a Reconfigurable Multiplier with Variable-Precision

Sang Hyun Ahn; Seung Bum Baek; Kyoung Rok Cho

doi:10.23075/jicas.2020.6.1.002

Sang Hyun Ahn Chungbuk National University
Seung Bum Baek Chungbuk National University
Kyoung Rok Cho Chungbuk National University

DOI: https://doi.org/10.23075/jicas.2020.6.1.002

Keywords: Arithmetic Unit, Digital SoC, Multiplier, Reconfigurable, Variable-Precision

Abstract

Multipliers remain as a key computational element in numerous high-performance digital systems including the upcoming Machine Learning (ML) hardware and contribute to the overall performance of the system. In this paper, we introduce a variable-precision reconfigurable multiplier and compare the performance against the more conventional fixed-precision multiplier in terms of power dissipation and propagation delay by deploying an FIR filter as our test-bed. The proposed multiplier has enhanced performance in terms of power reduction by 64%, area reduction by 48% and furthermore 60% improvement in propagation delay behavior. The reconfigurable multiplier was implemented using Magnachip / SK Hynix 0.35um process and a 3.3V supply voltage. An FPGA Basys3(xc7a35tcpg-236L) board was used to verify the performance and function of the parallel operation of the proposed multiplier. The Result was a 4-bit input through the FPGA and a chip. The result from that input represents the propagation delay of the multiplier operation, results indicated a worst-case propagation delay for 22.5ns.

Author Biographies

Sang Hyun Ahn, Chungbuk National University

Sang Hyun Ahn is currently working toward the M.S degree in the Department of Information and Communication Engineering, Chungbuk National University, Cheongju, South Korea. His reasearch interests are in the field of Artificial Intelligence and Communication Circuit Design.

Seung Bum Baek, Chungbuk National University

Seung Bum Baek received the B.S. and M.S. degrees in information and communication engineering from Chungbuk National University, Cheongju, South Korea, in 2015 and 2017, respectively, where he is also currently pursuing the Ph.D. degree. His current research interests include VLSI design for security services targeting resource-constrained devices, mathematical modeling for biomedical engineering applications, and embedded systems.

Kyoung Rok Cho, Chungbuk National University

Kyoung Rok Cho (S’89M’92) received the B.S. degree in electronic engineering from Kyoungpook National University, Taegu, Korea, in 1977 and the M.S and Ph.D. degree in electrical engineering from University of Tokyo, Tokyo, Japan, in 1989 and 1992, respectively. From 1979 to 1986, he was with the TV Research Center, LG Electronics, Seoul, South Korea. In 1999 and 2006, he was with Oregon State University, Corvallis, OR, USA, as a Visiting Scholar. He is currently a Professor at the College of Electrical and Computer Engineering, Chungbuk National University, Cheongju, South Korea, where he is also the Director of the IC　Design Education Center. His SoC platform design for communication system, and prospective CMOS image sensor, memristor-based circuit, and the design of multilayer system on-systems technology. He is currently a Professor in the College of Cheongju, Korea, where he is also a Director of the World Class University program.