A 2.4 GHz Fractional-N Sub-Sampling PLL with a Hybrid Type Phase-Interpolator

Van Thai Dang; Myeong Gyu  Yang; Kwang Hyun Baek

doi:10.23075/jicas.2021.7.3.001

Van Thai Dang Chung-Ang University
Myeong Gyu Yang Chung-Ang University
Kwang Hyun Baek Chung-Ang University

DOI: https://doi.org/10.23075/jicas.2021.7.3.001

Keywords: Digital-to-Time Converter(DTC), Fractional-N, Least-Mean Square(LMS), Phase-interpolator, Phase Locked Loop(PLL), Sub-sampling

Abstract

This paper presents a 2.4 GHz sub-sampling fractional-N PLL (SSPLL) with a hybrid type phase-interpolator (HPI). The usage of the HPI alleviates the demanding specification of digital-to-time converter (DTC). The proposed HPI structure is composed of a capacitive and tournament phase-interpolator (PI). This structure generates multi-phases with lower power consumption due to the capacitive PI part which do not consume the static power. On the other hand, the capacitive PI is affected by mismatches and parasitic when generating a fine resolution. In order to achieve accuracy with lower power consumption, MSB part is divided by capacitive PI and LSB part is divided by the tournament PI. The proposed SSPLL with the HPI is implemented by 65 nm CMOS process. It achieves 162 fs jitter, -247.3 dB figure-of-merit (FoM), and -47 dBc fractional spurs with a gain calibration circuit which is based on a least-mean-square (LMS) algorithm.

Author Biographies

Van Thai Dang, Chung-Ang University

Van-Thai Dang received the B.S. degrees at School of Electronics and Communications Engineering from Hanoi University of Industry (HAUI), Hanoi, Vietnam, in 2013, and the M.S. degree in Electrical and Electronics Engineering in 2018 from Chung-Ang University, Seoul, South Korea, where he is currently working toward the Ph.D. degree in Electrical and Electronic Engineering. He was with Samsung Electronics Vietnam (2013-2016) as a member in Research & Development Group. His current research interests include mixed-signal integrated circuit design, low-power dc-dc converter, energy harvesting systems.

Myeong Gyu Yang, Chung-Ang University

Myeong-Gyu Yang received the B.S. degrees at School of Electrical and Electronics Engineering from Chung-Ang University, Seoul, South Korea, in 2020, where he is currently working toward the M.S. degree in Electrical and Electronic Engineering. His current research interests include mixed-signal integrated circuit design, switched-capacitor dc-dc converter, energy harvesting systems.

Kwang Hyun Baek, Chung-Ang University

Kwang-Hyun Baek received the B.S. and M.S. degrees from Korea University, Seoul, Korea, in 1990 and 1998, respectively. He received the Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign (UIUC), IL, USA, in 2002. From 2000 to 2006, he was with the Department of High-Speed Mixed-Signal ICs as a senior scientist at Rockwell Scientific Company, formerly Rockwell Science Center (RSC), Thousand Oaks, CA, USA. At RSC, he was involved in development of high-speed data converters (ADC/DAC) and direct digital frequency synthesizers (DDFS). He was also with Samsung Electronics from 1990 to 1996. Since 2006 he has been with the School of Electrical and Electronics Engineering, Chung-Ang University (CAU), Seoul, Korea, where he is a faculty member. His research interests include high-performance analog and digital circuits such as low-power ADCs, high-speed DACs, hybrid frequency synthesizers (PLLs, DDFSs), high-speed interface circuits (CDRs, SerDes), PMIC, and near threshold-voltage (NTV) circuits.

Homepage : https://midaslab.cau.ac.kr/

A 2.4 GHz Fractional-N Sub-Sampling PLL with a Hybrid Type Phase-Interpolator

Abstract

Author Biographies

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