22.5 – 27GHz High Suppression Frequency Tripler with Excellent Output Power Flatness in 65-nm CMOS

  • Jeong Taek Son Department of Electronics Engineering, Chungnam National University
  • Han Woong Choi
  • Choul Young Kim
Keywords: 5G, CMOS, Frequency Multiplier, Harmonic Suppression, Tripler


This paper presents a high harmonic suppression frequency tripler with an excellent output power flatness in 65-nm CMOS process. In order to achieve a high first, second and forth harmonic suppression, the highly balanced different transformer is employed. The proposed tripler multiplies 7.5 9 GHz to 22.5 27 GHz with 1.5-dB ripple. It suppress the harmonic up to 40-dBc and consumes a DC power of 20 mW at a maximum operating point. The tripler occupies a 0.259x0.742 mm2.