Compact Noise and Linearity Model of a Dynamic Amplifier for Behavioral ADC Modeling
This paper introduces the behavioral model of dynamic amplifier which is designed in 28nm CMOS process. First, the gain of the dynamic amplifier is analyzed from various perspectives, such as input common mode voltage, input differential mode voltage and pulse width. Next, the method that is to implement the gain value non-linearity model of the amplifier and the noise model through SPICE simulations is described in detail. The gain model including nonlinearity exhibits –6.7%∼5.4% of modeling error rate and the noise model shows –11.2%∼13.5% of modeling error rate. The proposed in this paper model is applied to the 1.1Gs/s 7-bit pipelined ADC design verification to confirm the reliability. In addition, design efficiency of the proposed behavioral model is described.