Compact Noise and Linearity Model of a Dynamic Amplifier for Behavioral ADC Modeling

  • Sung Won Roh Konkuk University
  • Seon Kyeong Kim Konkuk University
  • Jin Tae Kim Konkuk University
Keywords: Behavioral Modeling, Dynamic Amplifier, Pipelined SAR ADC

Abstract

This paper introduces the behavioral model of dynamic amplifier which is designed in 28nm CMOS process. First, the gain of the dynamic amplifier is analyzed from various perspectives, such as input common mode voltage, input differential mode voltage and pulse width. Next, the method that is to implement the gain value non-linearity model of the amplifier and the noise model through SPICE simulations is described in detail. The gain model including nonlinearity exhibits –6.7%∼5.4% of modeling error rate and the noise model shows –11.2%∼13.5% of modeling error rate. The proposed in this paper model is applied to the 1.1Gs/s 7-bit pipelined ADC design verification to confirm the reliability. In addition, design efficiency of the proposed behavioral model is described.

Author Biographies

Sung Won Roh, Konkuk University

Sung Won Roh received the B.S. degrees in electrical engineering from Konkuk University, Seoul, Korea, in 2020. She is currently pursuing the M.S degree in electrical engineering from Konkuk University, Seoul, Korea. Her research interest includes CMOS integrated circuits and data converters.

Seon Kyeong Kim, Konkuk University

Seon Kyeong Kim received the B.S. M.S degrees in electrical engineering from Konkuk University, Seoul, Korea, in 2018 and 2020, respectively. Her research interest includes CMOS integrated circuits and data converters. Especially, she is currently conducting the research on pipeline SAR ADC.

Jin Tae Kim, Konkuk University

Jin Tae Kim received the B.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 1997, and the M.S. and Ph.D. degrees in electrical engineering from University of California, Los Angeles, CA, in 2004 and 2008, respectively.

He is an associate professor of Electronics Engineeing department at Konkuk Univeristy, Seoul, Korea. His current research focus is on high-performance and low-power mixed-signal integrated circuit (IC) designs in advanced CMOS technologies and computer-aided design methodologies for analog and mixed-signal ICs. He has held various industry positions at Xeline, Seoul, Korea, Barcelona Design, Sunnyvale, CA, Keysight Technologies, Santa Clara, CA (Formerly part of Agilent Technology), SiTime Corporation, Sunnyvale, CA, and Invensense Technology, San Jose, CA, where he was involved in the design of numerous communication and sensor IC products. Dr.Kim is a recipient of the IEEE Solid-State Circuits Predoctoral Achievement Award in 2007-2008.

Published
2020-12-31
How to Cite
Roh, S. W., Kim, S. K., & Kim, J. T. (2020). Compact Noise and Linearity Model of a Dynamic Amplifier for Behavioral ADC Modeling. Journal of Integrated Circuits and Systems, 7(1). https://doi.org/10.23075/jicas.2021.7.1.003
Section
Articles