Design of a 6-bit Broadband Differential Digital Attenuator Using a Hybrid Topology for DC–13 GHz Systems

Abstract

This paper presents the design and implementation of a 6-bit differential digital step attenuator targeting broadband transmitter applications across the DC–13 GHz range. The circuit is fabricated using a 0.13-????m SiGe BiCMOS process and achieves high-resolution attenuation with minimal insertion loss variation across 64 discrete control states. A hybrid topology is employed to optimize performance across all attenuation bits: bridged-T-type topologies are used for the 16 dB and 8 dB bits to ensure flat insertion loss in high-attenuation states; π-type topologies are adopted for the 4 dB and 2 dB bits to achieve compact layout and balanced signal paths; and MOSFET-based resistive shunt switches are utilized for the 1 dB and 0.5 dB bits, enabling fine resolution without discrete resistors. The attenuator operates in fully differential mode to match system-level signal interfaces. Simulation results confirm an RMS amplitude error below 1 dB and an RMS phase error under 16° across the DC–13 GHz frequency range. Embedded matching inductors are used to compensate for the parasitic capacitance of MOSFET switches, enhancing return loss performance. The average input and output return losses are –21.84 dB and –15.11 dB, respectively. The total chip area including pads is 1030 × 510 μm².