A V-Band CMOS Frequency Doubler in 65 nm CMOS
Keywords:
60 GHz, CMOS, conversion gain, efficiency, frequency doubler, fundamental rejection, millimeter-wave, multiplier, output power, V-band.
Abstract
Abstract – This article introduces a high output power and high conversion gain millimeter-wave CMOS frequency doubler. The frequency doubler adopts the optimum transistor size and gate bias voltage to achieve high output power, high conversion gain and high efficiency. The measured results demonstrate a peak conversion gain (CG) of 1.45 dB, a peak DC-to- RF efficiency of 11.26 % and a saturated output power of 5.65 dBm at 63 GHz. At the peak CG, the 3-dB bandwidth is 8.9 GHz from 57 to 65.9 GHz. The fundamental rejection is larger than 10.75 dB in 57 to 66 GHz. The chip area, including RF and DC pads, was 0.4 * 0.5 mm2 in 65-nm CMOS process. The power consumption is 12 mW at an input power of 0 dBm.
Published
2024-07-01
How to Cite
Yoo, I. C., Cho, D. O., & Byeon, C. W. (2024). A V-Band CMOS Frequency Doubler in 65 nm CMOS. Journal of Integrated Circuits and Systems, 10(3). https://doi.org/10.23075/jicas.2024.10.3.008
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Articles
