A Proposal of Methodologies for Implementing Digital Chips in the Latest Processes

Hye-Seung Sun; In-Shin Cho

doi:10.23075/jicas.2024.10.2.008

Hye-Seung Sun University of Korea Polytechnics
In-Shin Cho Integrated Circuit Design Education Center, Korea Advanced Institute of Science and Technology

DOI: https://doi.org/10.23075/jicas.2024.10.2.008

Keywords: Methodology, Digital ASIC

Abstract

In this paper, design methodologies suitable for implementation of digital systems at various processes are suggested. Important issues about Multi Corner Multi Mode, Hierarchical Design, adoption of CCS model, and changes in design flow must be considered at ultra-fine processes. The Cortex-M0 SoC Platform is implemented with considering important issues and the results using various digital libraries are compared.

All implemented platforms meet specifications and operate normally with hardware and software. The fastest clock cycle that can be synthesized is 4ns for Samsung 28nm

Author Biographies

Hye-Seung Sun, University of Korea Polytechnics

Hye-Seung Sun received the B.S. degree in information and communication engineering from Hanbat National University, Daejeon, Korea, in 2007, and the M.S. degree in computer engineering from the same university in 2009. His research interests include digital ASIC design flow, with a current focus on low-power IC design for ARM Cortex SoC Platform.

In-Shin Cho, Integrated Circuit Design Education Center, Korea Advanced Institute of Science and Technology

In-Shin Cho received the B.S. degree in information and communication engineering from Hanbat National University, Daejeon, Korea, in 2005, and the M.S. degree in computer engineering from the same university in 2007. His research interests include analog ASIC design flow, with a current focus on low-power IC design.