A 6.4Gbit/s 3-Tap High-Speed IO FIR Driver with  LMS Adaptation Algorithm in 65nm CMOS

Chankyu Yu; Seungwoo Shim; Taehyoun Oh

doi:10.23075/jicas.2024.10.2.005

Chankyu Yu Kwangwoon University
Seungwoo Shim Kwangwoon University
Taehyoun Oh Kwangwoon University

DOI: https://doi.org/10.23075/jicas.2024.10.2.005

Keywords: High-Speed IO, SerDes, Transceiver, FIR, Driver, variable gain amplifier, sigh-sign LMS

Abstract

A 6.4Gb/s IO transceiver including an adaptive finite impulse response (FIR) filter has been implemented with 65nm technology. The FIR tap coefficients are adapted using sign-sign least mean square (LMS) algorithm. Eye-openings are improved under time varying conditions by creating a diverse channel loss environment. The transceiver consumes 64mW/lane at 1.2V supply and the chip size is 0.506mm^2. The measured vertical eye-opening has been improved from 152.4mV/1.06V to 356.6mV/699.3mV after pre-emphasis and the measured horizontal eye-opening is 0.484 UI at BER.

Author Biographies

Chankyu Yu, Kwangwoon University

Chankyu Yu is currently pursuing a B.S. degree in electronics convergence engineering from Kwangwoon University, Seoul, South Korea. His current research interests include analog/mixed IC designs, especially IO interface transceiver circuits.

Seungwoo Shim, Kwangwoon University

Seungwoo Shim is currently pursuing a B.S. degree in electronics engineering from Kwangwoon University, Seoul, South Korea. His current research interests include analog/mixed IC designs especially IO interface transceiver circuits, and low-power high-frequency PLL designs.

Taehyoun Oh, Kwangwoon University

Taehyoun Oh (S’05) received the Bachelor of Science (B.S.) and Master of Science (M.S.) degrees in Electrical Engineering from Seoul National University in 2005 and 2007, respectively. He received his Ph.D. degree in Electrical Engineering from the University of Minnesota, Minneapolis under the supervision of Dr. Ramesh Harjani. His doctoral research is focused on high-speed I/O circuits and architectures. During the summer of 2010, he worked on I/O channel modeling at AMD Boston Design Center, MA. In the fall semester of 2011, he researched on I/O architecture and jitter budgeting of the link at Intel Corp., CA. From fall of 2012, he joined the IBM system technology group, NY. and worked on performance verification of high-speed decision feedback equalizer for server processors. Since spring of 2013, he joined at the department of electronic engineering in Kwangwoon university in Seoul, Korea as an assistant professor. His current research interest is focused on clock generation IC design.

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