Delay Study by Parasitic Capacitance Caused by Inverter Layout

Abstract

The propagation time can be obtained by using the rising edge of the CLOCK signal reaching the receiver. To do this, it is necessary to synchronize the start time by synchronizing the impulse generator used in the transmitter and the Digital-to-Time Converter(DTC) part used in the receiver. In the receiver, the reference clock enters the delay line of the DTC. At this time, a template signal is generated by using a signal generated through each delay line. In addition, time information can be obtained by using the signal generated by the impulse generator of the receiver transmitted from the transmitter and whether the template signal is correlated with the correlator. Therefore, the DTC's delay line affects the resolution of time information.

Therefore, in this paper, we explain the difference and solution of the delay between the simulation in Schematic and the post-layout in the delay line of DTC.