A 0.89 μVrms Noise 93 dB High Dynamic Range Low Power 16 Channels Closed-Loop Neural Recording Chip

  • Jae Ouk Cho Korea Advanced Institute of Science and Technology
  • Jang Hwan Kim Korea Advanced Institute of Science and Technology https://orcid.org/0000-0002-5940-3475
  • Jun Tae Jang Korea Advanced Institute of Science and Technology
  • Hong Kyun Kim Korea Advanced Institute of Science and Technology https://orcid.org/0000-0002-2990-3583
  • Chul Kim Korea Advanced Institute of Science and Technology
DOI: https://doi.org/10.23075//jicas.2023.9.1.001
Keywords: Analog-to-digital converter(ADC), Closed-loop neural recording, Delta-sigma modulator(DSM)

Abstract

The closed-loop neural stimulation system's biggest concern is an artifact with more than tens of mV occurs due to stimulation. Previous studies have digitized the input signals through the analog-to-digital converter (ADC) after using amplifiers to measure tens of V neural signals. Since the amplifier reduces the input range, the amplifier's output is saturated when a large stimulation artifact appears. This chip design uses the 2nd-order continuous delta-sigma modulator (DSM) to measure signals without saturation even if stimulation artifacts are entered with the neural signal. Overall, circuit structures were designed with a focus on stable operation even if a sudden large signal came in. Also, it can quickly track the sudden change of signals by adding an auto-ranging algorithm. We present 16 channel neural recording chip with a 65-nm CMOS process and the entire chip area is 1 mm2 with 49W power consumption. Input-referred integrated noise from dc to 500 Hz was 0.89Vrms, and more than 93 dB input dynamic range were guaranteed.

Author Biographies

Jae Ouk Cho, Korea Advanced Institute of Science and Technology

Jae Ouk Cho received the B.S. degree in biomedical engineering from Hanyang University, Seoul, Korea, in 2019, and the M.S degree in bio and brain engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea in 2021. Currently, he is working toward Ph.D. degree in bio and brain engineering at KAIST, Daejeon, Korea. His research interests include Neural recording IC and implantable biomedical devices.

Jang Hwan Kim, Korea Advanced Institute of Science and Technology

Jang Hwan Kim received the B.S. degree in biomedical engineering from Korea University, Seoul, South Korea, in 2021, and is currently pursuing the M.S. degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. His research interests include the design and development of retinal prostheses as well as power-efficient neural stimulators with special focus on mixed signal circuits.

Jun Tae Jang, Korea Advanced Institute of Science and Technology

Jun Tae Jang received the B.S. degree in electrical engineering from Hanyang University, Seoul, Korea, in 2020. Currently, he is working toward M.S. degree in bio and brain engineering at KAIST, Daejeon, Korea. His research interests include Ultrasonic wireless power transfer system and power management ICs.

Hong Kyun Kim, Korea Advanced Institute of Science and Technology

Hong Kyun Kim received the B.S. degree in electrical engineering from Kyunghee University, Suwon, Korea, in 2016, and the M.S. degree from the Graduate School for Green Transportation Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2018. Currently, he is working toward Ph.D. degree in bio and brain engineering at KAIST, Daejeon, Korea. His research interests include wireless power transfer system and power management ICs.

Chul Kim, Korea Advanced Institute of Science and Technology

Chul Kim is an assistant professor in the Department of Bio and Brain Engineering and the Program of Brain and Cognitive Engineering at Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. He received the Ph.D. degree in 2017 from bioengineering, UC San Diego, La Jolla, CA, USA, where he was a postdoctoral fellow from 2017 to 2019. From 2009 to 2012, he was with SK HYNIX, Icheon, South Korea, where he designed power management circuitry for dynamic random-access memory. His current research interests include design of energy-efficient integrated circuits and systems for fully wireless brain-machine interfaces and unobtrusive wearable sensors.

He received a Gold Prize in the 16th Humantech Thesis Prize Contest from Samsung Electronics, Suwon, South Korea, in 2010, and the 2018 Shunichi Usami Ph.D. Thesis Design Award from the Bioengineering Department, UC San Diego. He was the recipient of a 2017, 2018 IEEE Solid-State Circuits Society Predoctoral Achievement Award. He served as a guest editor of IEEE Transactions on Biomedical Circuits and Systems (TBioCAS) for the special issue of ISCAS2020. Since 2020, he has served as an associate editor of TBioCAS, and as a technical program committee for IEEE Custom Integrated Circuits Conference (CICC). Prof. Kim is the co-editor of High-density integrated electrocortical neural interfaces: Low-noise low-power system-on-chip design methodology (Academic Press, 2019).

Homepage : https://beee.kaist.ac.kr/

Published
2023-04-01
How to Cite
Cho, J. O., Kim, J. H., Jang, J. T., Kim, H. K., & Kim, C. (2023). A 0.89 μVrms Noise 93 dB High Dynamic Range Low Power 16 Channels Closed-Loop Neural Recording Chip. Journal of Integrated Circuits and Systems, 9(2). https://doi.org/10.23075//jicas.2023.9.1.001
Issue
Vol 9 No 2 (2023)
Section
Articles

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