Word-line and Charge-pump modeling of NAND Flash using Standard CMOS Logic Process

  • Hyun Sik Jeong Korea Advanced Institute of Science and Technology
  • Seong Hwan Cho Korea Advanced Institute of Science and Technology
DOI: https://doi.org/10.23075/jicas.2021.7.4.008
Keywords: 3D NAND flash, Charge pump, High voltage regulator, Voltage step-up system, WL driver, Word line driver

Abstract

The industry has increased the word line layer to improve the density of 3D NAND flash. As the word line layer increases, the energy consumed to generate the boosted word line voltage has also increased. In 3D NAND flash, understanding the block configuration and operation of a voltage step-up system with high energy consumption should be preceded to implement a 3D NAND flash with low energy consumption.
This study presents a conventional voltage step-up system for triple-level cell 3D NAND flash to understand operation and classify energy consumption. The conventional voltage step-up system for a 56 word line layer is fabricated in 180nm UHV process and it consumes 141.15nJ from a 2.2V during 1 unit of program pulse and verify period.

Author Biographies

Hyun Sik Jeong, Korea Advanced Institute of Science and Technology

Hyunsik Jeong received the B.S. and M.S. degree in electrical engineering from Hanyang University, South Korea, in 2006 and 2008, respectively. He is currently pursuing the Ph.D. degree with the Korea Advanced Institute of Science and Technology, South Korea. His main interests are low-power and small area circuits for NAND Flash.

Seong Hwan Cho, Korea Advanced Institute of Science and Technology

SeongHwan Cho (Senior Member, IEEE) received the B.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 1995, and the M.S. and Ph.D. degrees in electrical engineering and computer science from the Massachusetts Institute of Technology, Cambridge, MA, USA, in 1997 and 2002, respectively. In 2002, he joined Engim, Inc., Acton, MA, USA, where he was involved in data converters and phased-locked loop design for the IEEE 802.11abg WLANs. From 2011 to 2012, he was a Research Scientist with Marvell Semiconductor, Inc., Santa Clara, CA, USA. From 2016 to 2017, he was a Research Scientist with Google, London, U.K. Since 2004, he has been with the Department of Electrical Engineering, KAIST, where he is currently a Professor. His current research interests include analog and mixed-signal circuits for low-power communication systems, health-care devices, and CMOS sensors. Dr. Cho has served on the Technical Program Committee for several IEEE conferences, including the International Solid-State Circuits Conference (ISSCC), the Symposium on very-large-scale integrated (VLSI), and the Asian Solid-State Circuits Conference. He was a co-recipient of the 2009 IEEE Transactions on Circuits and System Society Guillemin-Cauer Best Paper Award and the 2012 ISSCC Takuo Sugano Award for Outstanding Far-East Paper. He has twice received the Outstanding Lecturer Award from KAIST. He was an Associate Editor of the IEEE Journal of Solid-State Circuits and the IEEE Transcations on circuits and Systems. He was a Distinguished Lecturer of the IEEE Solid-State Circuits Society.

Homepage : https://ccs.kaist.ac.kr/

Published
2021-09-30
How to Cite
Jeong, H. S., & Cho, S. H. (2021). Word-line and Charge-pump modeling of NAND Flash using Standard CMOS Logic Process. Journal of Integrated Circuits and Systems, 7(4). https://doi.org/10.23075/jicas.2021.7.4.008
Issue
Vol 7 No 4 (2021)
Section
Articles