22.5 – 27GHz High Suppression Frequency Tripler with Excellent Output Power Flatness in 65-nm CMOS

  • Jeong Taek Son Chungnam National University
  • Han Woong Choi Chungnam National University
  • Choul Young Kim Chungnam National University
DOI: https://doi.org/10.23075/jicas.2021.7.2.001
Keywords: 5G, CMOS, Frequency Multiplier, Tripler, Harmonic suppression

Abstract

This paper presents a high harmonic suppression frequency tripler with an excellent output power flatness in 65nm CMOS process. In order to achieve a high first, second and forth harmonic suppression, the highly balanced different transformer is employed. The proposed tripler multiplies 7.5 - 9GHz to 22.5 - 27 GHz with ±1.5-dB ripple. It suppresses the harmonic up to 40-dBc and consumes a DC power of 20 mW at a maximum operating point. The tripler occupies a 0.259 × 0.742 mm2.

Author Biographies

Jeong Taek Son, Chungnam National University

Jeong Taek Son received the BS degree from Chungnam National University (CNU), Daejeon, Republic of Korea, in 2021, and is currently working toward a MS in Microelectronics Engineering from CNU. His research interests include RF/mm-wave integrated circuit design for wireless communications.

Han Woong Choi, Chungnam National University

Han Woong Choi received his MS from Chungnam National University (CNU), Daejeon, Republic of Korea, in 2017, and is currently working toward a Ph.D. in Microelectronics Engineering from CNU. His research interests include RF/mm-wave integrated circuits and systems for short-range radar and phased-array antenna applications.

Choul Young Kim, Chungnam National University

Choul Young Kim received his MS and Ph.D. from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea, in 2004 and 2008, respectively. From March 2009 to February 2011, he was a postdoctoral research fellow at the Department of Electrical and Computer Engineering, University of California, San Diego, USA. Currently, he is a Professor of Electronics Engineering at Chungnam National University. His research interests include RF/mm-wave integrated circuits and systems for short-range radar and phased-array antenna applications, and analog front-end readout integrated circuits for LADAR applications.

Homepage : https://sites.google.com/view/scdlab/home

Published
2021-04-01
How to Cite
Son, J. T., Choi, H. W., & Kim, C. Y. (2021). 22.5 – 27GHz High Suppression Frequency Tripler with Excellent Output Power Flatness in 65-nm CMOS. Journal of Integrated Circuits and Systems, 7(2), 1-5. https://doi.org/10.23075/jicas.2021.7.2.001
Issue
Vol 7 No 2 (2021)
Section
Articles