Design of a 12 – 14.5 GHz Digitally-Controlled Oscillator for Ultra-low-jitter PLL

  • Joo Eun Bang Korea Advanced Institute of Science and Technology
  • Yong Woo Jo Korea Advanced Institute of Science and Technology
  • Seo Jin Choi Korea Advanced Institute of Science and Technology
  • Jae Hyuk Choi Korea Advanced Institute of Science and Technology
DOI: https://doi.org/10.23075/jicas.2021.7.1.004
Keywords: Delta-Sigma Modulator(DSM), Digital-to-Analog Converters(DAC), Digitally-Controlled Oscillator(DCO), LC-VCO, Phase-Locked Loop, Phase noise, Sub-sampling

Abstract

The DCO was designed for the ultra-low-jitter digital sub sampling PLL. To suppress the enormous amount of quantization noise, very fine frequency resolution is critical. Also, phase noise of the LC VCO itself is crucial for ultra-low-jitter applications. For the high-performance LC VCO design, understanding of the basic insight of the oscillator is needed. The DCO consists of string type RDAC, MASH 1-1 DSM, and CMOS-type cross coupled LC VCO. The frequency resolution is significantly increased by using DSM. The proportional path has the resolution of 17-bit, while the integral path has the resolution of 18-bit. The DSM is operating at 400MHz and its quantization noise is canceled by the 2nd order low pass filter at the output of the DAC. By adopting 2nd order noise shaping, quantization noise at PLL out is negligible. The DAC designed with a string resistor topology for its design simplicity and relieved target specifications. The DCO has 12-14.5GHz of frequency tuning range. The phase noise at 1MHz offset frequency is -109dBC/Hz at 14GHz output. The average power consumption is 5.5mW. Calculated FOM at 1MHz offset frequency is -184.5dB.

Author Biographies

Joo Eun Bang, Korea Advanced Institute of Science and Technology

Joo Eun Bang (S’18) was born in Busan, South Korea, in 1995. She received the B.S. and M.S. degrees in electrical engineering from the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2018 and 2020, respectively. She is currently pursuing the Ph.D. degree with the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. Her current research interests include low-power and high-performance analog, mixed signal, and RF integrated circuits for emerging wireless/wired standards.

Yong Woo Jo, Korea Advanced Institute of Science and Technology

Yong Woo Jo (S’17) was born in Gumi, South Korea, in 1995. He received the B.S. and M.S. degrees in electrical engineering from the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2018 and 2020, respectively. He is currently pursuing the Ph.D. degree at the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. His current research interests include digital PLL and RF integrated circuits for next generation communications.

Seo Jin Choi, Korea Advanced Institute of Science and Technology

Seo Jin Choi (S’14) was born in Seoul, Korea, in 1991. She received the B.S. and ph.D degrees in electrical engineering from Ulsan National Institute of Science and Technology (UNIST), Korea, in 2015 and 2020, respectively. She is the recipient of 2016 ISSCC Silkroad award. Her research interests include analog/mixed IC designs, especially innovative clock generation circuits.

Jae Hyuk Choi, Korea Advanced Institute of Science and Technology

Jae Hyouk Choi (S’06–M’11) was born in Seoul, South Korea, in 1980. He received the B.S. degree (summa cum laude) in electrical engineering from Seoul National University, Seoul, South Korea, in 2003, and the M.S. and Ph.D. degrees in electrical and computer engineering from Georgia Institute of Technology, Atlanta, GA, USA, in 2008 and 2010, respectively. From 2010 to 2011, he was with Qualcomm, Inc., San Diego, CA, USA, where he was involved in designing multi-standard cellular transceivers. In 2012, he joined the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, and served as a faculty member. Since 2019, he has been an Associate Professor at the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. Dr. Choi has been a TPC member of the IEEE ISSCC since 2017 and the IEEE ESSCIRC since 2016. He was the country representative of Korea for the ISSCC Far-East region in 2018. His research interests include low-power and high-performance analog, mixed signal, and RF integrated circuits for emerging wireless/wired standards.

Homepage : https://www.icsl.snu.ac.kr/

Published
2020-12-31
How to Cite
Bang, J. E., Jo, Y. W., Choi, S. J., & Choi, J. H. (2020). Design of a 12 – 14.5 GHz Digitally-Controlled Oscillator for Ultra-low-jitter PLL. Journal of Integrated Circuits and Systems, 7(1). https://doi.org/10.23075/jicas.2021.7.1.004
Issue
Vol 7 No 1 (2021)
Section
Articles