A 20-Gb/s/pin Single-Ended Transmitter with Capacitive Peaking Driver Based Crosstalk and Inter-Symbol Interference Compensation

Abstract

This paper presents a 20-Gb/s/pin single-ended transmitter that employs a capacitive peaking driver (CPD)- based crosstalk and inter-symbol interference (ISI) compensation technique, implemented in a 65-nm CMOS process. The CPD enhances high-frequency signal components and plays a central role in suppressing crosstalk and ISI, while its programmable capacitor bank enables adaptation to a wide range of channel-loss conditions. By generating the crosstalk compensation signal in advance from low-rate data of adjacent lanes, the proposed architecture achieves zero latency and aligns the shaping action with the expected disturbance window while incurring minimal power overhead, eliminating the need for highest-rate replica paths. Digitally controlled delay lines (DCDLs) further refine the timing of both crosstalk and ISI compensation. Post-layout simulation results demonstrate a horizontal eye-opening of 31.22 ps and a vertical eye-opening of 18.14 mV under a worst-case channel condition exhibiting 25.89 dB insertion loss at the Nyquist frequency. These results confirm that the CPD-based compensation scheme effectively mitigates crosstalk and ISI while maintaining energy-efficient high-speed signaling, making it a promising solution for future low-power, high-bandwidth serial interfaces.