Design of a 2nd-Order Noise-Shaping SAR ADC Using Cascaded Floating Inverter Amplifiers

Abstract

This paper presents a 2nd-order noise-shaping successive approximation register (NS-SAR) ADC employing cascaded floating inverter amplifier (FIA) integrators. Key design considerations for the cascaded FIA-based loop filter are systematically analyzed and incorporated into the proposed architecture. The ADC is designed to achieve stable loop dynamics and enhanced noise-shaping efficiency while maintaining low power consumption. The chip was designed in a TSMC 0.18 μm standard CMOS process and achieves 83.98 dB SNDR, 89.15 dB SFDR, and a dynamic range of 83.04 dB while consuming 81.13 μW at a 2-MHz sampling rate with an oversampling ratio of 256, corresponding to a Schreier figure-of-merit of 160.80 dB.