Design of an Energy-Efficient Neuron Circuit with Temporal Encoding for Capacitive Coupling Based Compute-In Memory Technology

Jung Nam Kim; Minsuk Koo; Yoon Kim

doi:10.23075/jicas.2025.11.4.008

Jung Nam Kim Department of Electrical and Computer Engineering, University of Seoul;Center for Semiconductor Research, University of Seoul
Minsuk Koo School of Advanced Fusion Studies, University of Seoul;Center for Semiconductor Research, University of Seoul;IM Electronics co.
Yoon Kim Department of Electrical and Computer Engineering, University of Seoul;Center for Semiconductor Research, University of Seoul;IM Electronics co.

DOI: https://doi.org/10.23075/jicas.2025.11.4.008

Keywords: Capacitive Coupling, Compute-In Memory, Matrix-Vector Multiplication

Abstract

Matrix-vector multiplication (MVM) is a core operation in large language models (LLMs), and compute-inmemory (CIM) technologies offer a promising path to overcome data movement bottlenecks. Among them, capacitive coupling principle-based CIM (CCP-CIM) enables low-power operation by eliminating static current paths. In this work, we propose an energy-efficient neuron circuit optimized for CCPCIM. The design features a cascaded input stage for enhanced transconductance linearity, as well as feedback-assisted control and overflow/underflow detection to reduce unnecessary digital conversions. Furthermore, the discharge rate is dynamically adjustable through analog biasing, enabling flexible control of the neuron’s response range. Implemented in TSMC 28 nm CMOS, the proposed design achieves up to 2.15× less energy consumption than a conventional neuron circuit. This work supports scalable and adaptive analog inference for edge AI applications.