Four-Phase Always Quadra-Path Hybrid DC-DC Converter with Output Capacitor Free

Seokjin Kim; Chulwoo Kim

doi:10.23075/jicas.2025.11.3.009

Seokjin Kim Korea University
Chulwoo Kim Korea University

DOI: https://doi.org/10.23075/jicas.2025.11.3.009

Keywords: Hybrid DC–DC converter, multi-path, step-down converter

Abstract

This paper presents a four-phase always quadra-path (AQP) DC–DC converter designed to achieve high power density and power conversion efficiency with low output ripple. The proposed architecture consists of one inductor path and three capacitor paths operating in a time-interleaved manner to collectively deliver the output current. This structure reduces the inductor’s DC current stress, enabling the use of a compact inductor without sacrificing efficiency or transient performance. The converter supports an output voltage range of 0.3–2.0 V from a 5 V input supply, making it suitable for battery-powered and low-voltage SoC applications. The hybrid current delivery through capacitive and inductive paths improves transient response and ripple suppression. Measurement results show a peak power conversion efficiency (PCE) of 74% and a maximum load current of 2 A. The converter is implemented in a TSMC 180 nm BCD process, occupying a 3 mm × 3 mm (9 mm²) silicon area.

Author Biographies

Seokjin Kim, Korea University

Seokhjin Kim (Graduate Student Member, IEEE) received the B.S. in electrical engineering at Korea University, Seoul, South Korea, in 2023, where he is currently pursuing the M.S. degree.

His research interests include integrated power management system designs and low-power CMOS analog circuit designs, and DC-DC power converter.

Chulwoo Kim, Korea University

Chulwoo Kim (Senior Member, IEEE) received the B.S. and M.S. degrees in electronics engineering from Korea University in 1994 and 1996, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 2001.

In May 2001, he joined the IBM Microelectronics Division, Austin, TX, where he was involved in Cell processor design. Since September 2002, he has been with the School of Electrical Engineering, Korea University, where he is currently a Professor. He was a Visiting Professor at the University of California at Los Angeles in 2008 and at the University of California at Santa Cruz in 2012. He is a co-author of two books, namely, CMOS Digital Integrated Circuits: Analysis and Design (McGraw-Hill, 4th edition, 2014) and High-Bandwidth Memory Interface (Springer, 2013). His current research interests are in the areas of wireline transceiver, power management, data converters, and quantum-inspired computing.

Dr. Kim received the Samsung HumanTech Thesis Contest

Bronze Award (1996), the ISLPED Low-Power Design Contest Award (2001, 2014), the DAC Student Design Contest Award (2002), SRC Inventor Recognition Awards (2002), the Young Scientist Award from the Ministry of Science and Technology of Korea (2003), the Seoktop Award for excellence in teaching (2006, 2011, 2018, 2023) and ASP-DAC Best Design Award (2008) and Special Feature Award (2014), Korea Semiconductor Design Contest: Prime Minister’s Award (2016). He served on the Technical Program Committee of the IEEE International Solid-State Circuits Conference and as a Guest Editor for the IEEE Journal of Solid-State Circuits. He also served as the Chair of the SSCS Seoul Chapter and as the Distinguished Lecturer of the IEEE Solid-State Circuits Society for 2015-2016. He is currently on the editorial boards of the IEEE Journal of Solid-State Circuits and Transactions on VLSI Systems and is an elected AdCom member of the IEEE Solid-State Circuits Society.

Homepage : https://kilby2.korea.ac.kr/