A 5-GHz Multi-Modulus Divider with Duty Cycle Extension Re-Timer on 65-nm CMOS Technology

Jongwon Moon; Minjae Lee

doi:10.23075/jicas.2025.11.3.007

Jongwon Moon Gwangju Institute of Science and Technology
Minjae Lee Gwangju Institute of Science and Technology

DOI: https://doi.org/10.23075/jicas.2025.11.3.007

Keywords: Phase locked loop, divider, re-timer, MMD, duty-cycle

Abstract

In this paper, a multi-modulus divider (MMD) operating at 5 GHz has been designed using a 65-nm CMOS process. The MMD core is composed of cascaded DIV2/3 cells. The first three stages were composed of TSPC D-flipflop, and the last stage was composed of static D-flipflop. We propose a re-timer that extends the duty cycle by generating an asynchronous reset through digital logic gates. This not only removes accumulated circuit noise, but also generates a duty cycle from at least 43% to 53% depending on the division ratio. Based on the output frequency of 200MHz, when N is 25, the total power consumption is 0.9mW, and the circuit size is 75μm*30.5μm.

Author Biographies

Jongwon Moon, Gwangju Institute of Science and Technology

Jongwon Moon received the B.S. degree in information, communications, and electronic engineering from Catholic University of Korea, Bucheon, Korea, in 2022. He is currently pursuing the integrated M.S. and Ph.D. degree in electrical engineering and computer science with Gwangju Institute of Science and Technology (GIST), Gwangju, Korea. His research interests include digitally controlled oscillators and low-noise digital phase-locked loop.

Minjae Lee, Gwangju Institute of Science and Technology

Minjae Lee received the B.Sc. and M.S. degrees in electrical engineering from Seoul National University, Seoul, South Korea, in 1998 and 2000, respectively, and the Ph.D. degree in electrical engineering from the University of California at Los Angeles, Los Angeles, CA, USA, in 2008.

In 2000, he was a Consultant with GCT Semiconductor Inc., San Jose, CA, USA, and Silicon Image Inc., Sunnyvale, CA, USA, designing analog circuits for wireless communication and digital signal processing blocks for Gigabit Ethernet. In 2001, he joined Silicon Image Inc., developing Serial ATA products. In August 2008, he joined Agilent Technologies, Santa Clara, CA, USA, where he was involved with the development of next-generation high-speed ADCs and DACs. Since 2012, he has been with the School of Electrical Engineering and Computer Science, Gwangju Institute of Science and Technology (GIST), Gwangju, South Korea, where he is currently a professor.

Dr. Lee received the Best Student Paper Award at the Symposium on VLSI Circuits, Kyoto, Japan, in 2007, and the GIST Distinguished Lecture Award in 2015.

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