MV – HEVC Chip Design Using High Level Synthesis

Abstract

This study proposed a system that MV-HEVC design using High-Level Synthesis(HLS). There are several improvements in MV-HEVC Design. First of all, using HLS tool enables designers to quickly verify feasibility of different hardware-software boundaries. The system uses more than Mb size memory even in very small environment such as MV-HEVC. Instead of using memory inside the chip, it uses external memory, especially memory such as DDR1, which can operate at low speeds. IO is not specially designed for memory use, but to allow memory access using GPIO. Low power delay is implemented to control skew between data and memory control that can operate at low speed. The implementation of the algorithm made the chip through the Samsung 65nm foundry process. In conclusion, we designed hardware of MV-HEVC for real-time coding of multi-view video and improves and optimizes the coding speed through integrated design of SW / HW using SoC.  And also we designed a system that can use more than Mb of memory at low speeds, such as MV-HEVC environments.