Hardware-Software Co-Design for Analog Compute-in-Memory Accelerators Using 1-bit Sense Amplifiers

Jihwan Cho; Wanyeong Jung

doi:10.23075/jicas.2025.11.1.008

Jihwan Cho Korea Advanced Institution of Science and Technology (KAIST)
Wanyeong Jung Korea Advanced Institution of Science and Technology (KAIST)

DOI: https://doi.org/10.23075/jicas.2025.11.1.008

Keywords: Compute-in-memory (CIM), hardware- software co-design, analog computing, binary neural network (BNN)

Abstract

In this paper, we present a hardware-software co-design methodology for analog compute-in-memory (CIM) accelerators with 1-bit sense amplifiers (SAs). While CIM macro using 1-bit SAs achieves high energy efficiency by eliminating multi-bit analog-to-digital converters (ADCs), it faces two key challenges: limitations in BNN layer size and the impact of SA random noise. Through neural network splitting, which divides layers into sub-blocks matching the size of the CIM macro rows, the BNN model fits the CIM macro while preserving accuracy. Additionally, the SA output probability model is obtained through measurements and replaces the binarization function of BNN, incorporating SA random noise into the BNN training process. Using these two approaches, we develop a framework to retrain BNNs tailored to the CIM accelerator and achieve 97.81% MNIST inference accuracy on the prototype 128x128 CIM accelerator fabricated in 28 nm technology.

Author Biographies

Jihwan Cho, Korea Advanced Institution of Science and Technology (KAIST)

Jihwan Cho received the B.S. degree in electrical and electronics engineering from Chung-Ang University, Seoul, South Korea, in 2021, and the M.S. degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2023. He is currently pursuing the Ph. D. degree at Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea.

His research interests include low-power digital circuits and energy-efficient deep neural network accelerators.

Wanyeong Jung, Korea Advanced Institution of Science and Technology (KAIST)

Wanyeong Jung received the B.S. degree from Seoul National University, Seoul, South Korea, in 2012, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, in 2014 and 2017, respectively. He was a Research Intern with NVIDIA Research, Austin, TX, USA, in 2016. From 2017 to 2019, he was a Post -Doctoral Associate with Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA, USA. Since 2019, he has been an Assistant Professor with the School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea.

His research interests include low -power circuits and systems, energy -efficient edge computing, and Internet of Things (IoT).

Homepage : https://seed.kaist.ac.kr/home