Design of a 520-624-GHz Amplifier-Frequency-Doubler Chain in 250-nm InP HBT Technology
Abstract
In this study, an Amplifier-Frequency-Doubler Chain (AFDC) operating around 600 GHz has been designed based on 250-nm InP HBT technology. It consists of a 300-GHz drive amplifier followed by a 600-GHz frequency doubler. The drive amplifier adopts a four-stage cascode topology, in which a staggering matching scheme is used to achieve a wide bandwidth. Additionally, to saturate the subsequent frequency doubler, load-pull matching is adopted for the output matching of the amplifier. The frequency doubler is based on a push-push topology followed by an output matching network that helps to suppress the undesired fundamental and odd-order harmonics. The integrated AFDC exhibited a simulated peak output power of -8.4 dBm, with a 3-dB bandwidth of 104 GHz (520-624 GHz), or a fractional bandwidth of 20.7% at 0-dBm input power. The simulated total DC power consumption is 282.6 mW. The layout size is 1137 X 464 mm², including probing pads.